1. Field of the Disclosure
The disclosure relates to an array substrate for a display device, and more particularly, to an array substrate for a display device including a thin film transistor and a method of manufacturing the same.
2. Discussion of the Related Art
With rapid development of information technologies, various display devices for displaying images have been requested. Flat panel display (FPD) devices such as a liquid crystal display (LCD) device, a plasma display panel (PDP) device and an organic light emitting diode (OLED) device have been suggested.
Among the FPD devices, the LCD device has been widely used for its superiorities of small size, light-weight, thin profile and low power consumption.
An active matrix type display device, which includes pixels arranged in a matrix form and switching elements for controlling on/off the respective pixels, have been widely used. The active matrix type display device includes an array substrate, on which gate lines, data lines, switching elements and pixel electrodes are formed. The array substrate will be described hereinafter with reference to accompanying drawings.
FIG. 1 is a plane view of illustrating an array substrate for a display device according to the related art.
In FIG. 1, a gate line 22 and a data line 52 cross each other to define a pixel region P. A thin film transistor T is connected to the gate line 22 and the data line 52.
The thin film transistor T includes a gate electrode 24, an active layer 42, a source electrode 54 and a drain electrode 56. The gate electrode 24 is connected to the gate line 22, the source electrode 54 is connected to the data line 52, and the drain electrode 56 is spaced apart from the source electrode 54. The active layer 52 is exposed between the source electrode 54 and the drain electrode 56, and the exposed portion of the active layer 52 becomes a channel of the thin film transistor T.
A pixel electrode 72 is formed in the pixel region P and is connected to the drain electrode 56 of the thin film transistor T through a drain contact hole 62.
A cross-sectional structure of an array substrate for a display device according to the related art will be described with reference to FIG. 2.
FIG. 2 is a cross-sectional view of illustrating an array substrate for a display device according to the related art and corresponds to a cross-section taken along the line II-II of FIG. 1.
In FIG. 2, a gate line 22 and a gate electrode 24 connected to the gate line 22 are formed on a substrate 10, and a gate insulating layer 30 is formed on the gate line 22 and the gate electrode 24.
An active layer 42 of intrinsic silicon is formed on the gate insulating layer 30 over the gate electrode 24, and ohmic contact layers 44 of impurity-doped silicon are formed on the active layer 42.
A data line 52, a source electrode 54 and a drain electrode 56 are formed on the ohmic contact layer 44. A passivation layer 60 is formed on the data line 52, the source electrode 54 and the drain electrode 56. The passivation layer 60 includes a drain contact hole 62 exposing the drain electrode 56.
A pixel electrode 72 is formed on the passivation layer 60 and is connected to the drain electrode 56 through the drain contact hole 62.
Recently, as the display devices have been requested to have large sizes and high definitions, lengths of signal lines such as the gate line 22 and the data line 52 become longer. Thus, resistances of the signal lines increases, and signal delays are caused. In addition, since driving speeds are heightened, loads applied to the signal lines are raised. To solve these problems, various attempts have been made.
For example, the resistance of the signal line can be decreased by widening a width of the signal line. In this case, since an area of the pixel region is decreased, an aperture ratio is reduced and brightness is lowered. Here, the brightness may be raised by increasing an amount of provided light. However, power consumption is lifted, and light efficiency is lowered.
Alternatively, the resistance of the signal line may be decreased by thickening a thickness of the signal line. However, the signal line is formed by depositing a metallic material to form a metallic layer and selectively patterning the metallic layer. Thus, to thicken the thickness of the signal line, the metallic layer should be thickened, and an amount of the metallic material for deposition is increased. Moreover, an amount of an etchant for patterning the metallic layer is increased. Accordingly, the manufacturing costs of the array substrate are raised.
Meanwhile, certain metallic materials have poor properties in contact with the substrate, and when it is formed to be thick, it may be cracked or peeled off from the substrate. Therefore, there is a limitation on increasing the thickness of the signal line.